1. Field of the Invention
The present invention relates to a processor, ASIC and SOC having an on-chip memory for use in a case where access to an external memory as a specific region is repeated and, more particularly, to an information processing device having a function of displaying a screen on an image display device such as an LCD or a CRT.
2. Description of the Related Art
For displaying images on such a screen as an LCD (Liquid Crystal Display) or a CRT (Cathode Ray Tube), data is read from a memory called a frame buffer which stores information about luminance and color corresponding to each pixel and applied to the LCD or the CRT. Access to the frame buffer is ordinarily repeated 60 to 75 times a second.
With a simple structure, when a write access to a frame buffer at the time of rewriting a screen (at the time of information updating) and a read access to apply data from the frame buffer to an LCD or a CRT compete with each other, the screen will be disturbed. Therefore, it is a common practice to prepare frame buffers for two or more screens to switch and use a write side buffer and a read side buffer. Such a buffer structure is called double-buffer structure.
On the other hand, recent application processors for a portable terminal having an image displaying function have an LCD controller for image output, a DMA controller for data transfer, a processor or a DSP for image processing, and an on-chip memory integrated into one chip for increasing application performance and integration density and because of constraints on packaging.
FIG. 10 is a block diagram showing a structure of a conventional and typical application processor. With reference to FIG. 10, integrated on a chip of a conventional application processor are a processor core 1001, a peripheral active core 1002, an LCD display control device 1003, an on-chip memory 1004, a peripheral passive core 1005 and a core of a memory interface 1006. These are connected with each other through an on-chip address bus 1007 and an on-chip data bus 1008. The LCD display control device 1003 is connected to an LCD panel 1009 outside the chip. The memory interface 1006 is connected to an external memory 1010 outside the chip.
The processor core 1001 may have an on-chip cache within the core in some cases.
The on-chip memory 1004, whose application is determined by software or the like, is used as a program code region, a work region or a frame buffer region.
The LCD display control device 1003, which holds information about a start address of a frame buffer and a frame buffer size in an internal register (not shown), reads data from a frame buffer disposed on the on-chip memory 1004 or the external memory 1010 in accordance with a display speed of the LCD panel 1009 and applies the same to the LCD panel 1009.
When the frame buffer has a double-buffer structure, the LCD display control device 1003 holds addresses of two or more frame buffers and sets a frame buffer for use in displaying an image by means of the processor core 1001. Then, when rewriting an image, display of an image having no distortion such as flicker is realized by changing the setting.
FIG. 11 is a diagram for use in explaining screen switching. In this example, there are two frame buffers, frame buffers A and B. When one is used for generating new image data, the other is used for displaying an image. Frame buffer for use in generating image data is referred to as a drawing frame buffer and a frame buffer for use in displaying an image is referred to as a display frame buffer. Drawing frame buffer and a display frame buffer are alternately switched.
This allows, in line with application of data of 60 screens a second to the LCD panel 1009 by the LCD display control device 1003 by using one frame buffer, the processor core 1001, for example, to generate data of a new image in other frame buffer.
With reference to FIG. 11, frame buffer switching is conducted every 67 ms ( 1/15 second). First, the LCD display control device 1003 uses the frame buffer A disposed in the external memory 1010 as a display frame buffer to display data. Since the LCD panel 1009 needs to display an image once in about 16 ms, the LCD display control device 1003 reads the data of the frame buffer A several times repeatedly and applies the same to the LCD panel 1009. In the meantime, with the frame buffer B disposed in another address space of the external memory 1010 as a drawing frame buffer, the processor core 1001 draws an image to be displayed there next. After a lapse of 67 ms, the frame buffer B will serve as a display frame buffer and the frame buffer A will serve as a drawing frame buffer.
In recent years, an increase in a screen size and in the number of display colors is followed by an increase in the number of accesses to a frame buffer, so that these accesses make bus congestion conspicuous.
While the on-chip memory 1004 allows high-speed access, its capacity is limited due to constraints on chip area. Allocation of a plurality of frame buffers to the on-chip memory 1004 is accordingly difficult.
In practice, the on-chip memory 1004 is used as an instruction memory or a temporary work region for working when a high-load application requiring processing of a large amount of data is executed. Then, when necessary, data is transmitted and received between the on-chip memory 1004 and the external memory 1010. By arranging data whose access frequency is high in the on-chip memory 1004 to reduce the number of accesses to the external memory 1010 whose access speed is low, processing speed can be increased as a whole.
Methods of exchanging data between the external memory 1010 and the on-chip memory 1004 include a method conducted implicitly by hardware for software as by a cache memory which will be described later and activating a DMA controller by software.
Cache memory technique, which uses locality of an address as an access destination in a program code, is to realize speed up as a whole by copying a part of the contents of a large amount of memory into a high-speed memory of a small amount by hardware. The cache memory technique is widely used in a microprocessor and the like.
In the cache memory technique, data referred to by a program and data in its proximity are copied in the lump into a high-speed memory, and an address of the copied data is held. Then, in a subsequent access, an address of an access destination and the held address are compared to supply data of the high-speed memory in place of the data of the large amount of memory when they coincide with each other.
A display control system which efficiently handles frame data by a cache memory has been conventionally well known (e.g. see Japanese Patent Laying-Open (Kokai) No. Heisei 9-190169).
FIG. 12 is a block diagram showing one example of a structure of a conventional display control system.
With reference to FIG. 12, the conventional display control system has a display controller 1207 and a CPU 1201 connected to a cache memory 1204 through a cache controller 1202. When data displayed on a CRP 1208 exists in the cache memory 1204, data of the cache memory 1204 is read in place of data of a frame buffer 1206b allocated to a part of a region of a memory 1206a. 
In this conventional example, further provided are two tags 1203a and 1203b of this cache memory. By selectively using the two tags 1203a and 1203b for an access from the CPU 1201 and for an access from the display controller 1207, simultaneous access from the CPU 1201 and the display controller 1207 is enabled. This realizes speed-up of access.
Thus, an advantage in using a cache memory is to benefit from a high-speed memory without specially rewriting software. Furthermore, by making data access adapted to a structure of the cache and optimizing data arrangement, a high-speed cache memory can be used to the best.
In a case where a cache memory is provided, an access address and an address of cached data need to be compared at every access. Therefore, hardware cost is increased and power consumption is increased as well.
In addition, depending on constraints on a capacity of a cache memory and the number of associations of a cache memory, when accessing data of the latter half of a frame buffer, data in the former half might be pushed out from the cache memory in some cases. In such a case, efficient use of a cache memory is impossible.
Use of an on-chip memory as a cache memory under hardware management makes it difficult to use the on-chip memory as a work memory when executing such high-load application as described above.
On the other hand, when executing an application requiring a small amount of memory, using the on-chip memory as a frame buffer memory enables the number of accesses to an external memory to be reduced, thereby reducing power consumption.
There are cases, however, where it is difficult to secure two frame buffer regions on an on-chip memory in terms of costs due to an increase in a screen size or the number of colorings. For developing 260,000 colors in the QVGA (320×240 dot) size, a frame buffer of about 170 Kbyte is required. For securing two frame buffers on an on-chip memory, memory whose capacity is as large as 340 Kbyte is required. Integrating the memory together with a work region of an application allocated to the on-chip memory into one chip will increase the chip area to invite an increase in costs.
On the other hand, with the method in which only a frame buffer for use in displaying is placed on an on-chip memory, processing of transferring drawn frame data from an external memory to an on-chip memory should be realized by means of software, resulting in increasing processing loads.